WireUnWired Research Lab · Semiconductor economics
Model the economics of a good die—not just the wafer.
Explore how chip dimensions, scribe streets, defect assumptions and wafer cost interact. Change one variable at a time, compare yield models, and see how sensitive cost per good die and wafer-level profit are to your assumptions.
Use die width, die height and scribe spacing to estimate gross dies before defect-related yield loss.
Compare a random-defect Poisson model with a Negative Binomial model that can represent defect clustering.
Change wafer cost and selling price to study wafer-level cost, revenue and margin sensitivity.
Silicon Economics Simulator
See how die size and defects impact your bottom line.
0.09 = Mature (Good) | 0.50 = New Process (Risky)
Silicon economics is a sensitivity problem: small changes in die geometry, defect assumptions and usable die count can materially change estimated cost per good die. This guide explains the assumptions behind the two yield models and the geometry inputs used in the simulator.
The Battle of Models: Poisson vs. Negative Binomial
The simulator offers two simplified statistical assumptions. Neither model is universally the most accurate: the useful choice depends on the defect pattern and on whether you have measured process data with which to calibrate it.
The Poisson Model (The “Rain” Theory)
The Poisson model assumes defects occur randomly and independently at a uniform average density. It is a useful baseline, but it does not represent spatial clustering or other sources of yield variation.
Intuition: each die is treated as having the same expected defect exposure for its area. The model does not know whether defects are concentrated in one region or spread unevenly across a wafer.
When to use it: use it as a baseline when a random, independent-defect assumption is reasonable. If defects cluster or defect density varies across dies, Poisson can underpredict yield, particularly for larger die areas. See the IEEE Technology Navigator overview of IC yield.
The Equation:
$$Y = e^{-A \cdot D_0}$$
The Negative Binomial Model (The “Cluster” Theory)
The Negative Binomial yield model is widely used to represent defect-density variation and clustering. Defects can be concentrated in particular regions, so the same average defect density can produce a different yield than the uniform-random Poisson assumption. Its clustering parameter must be chosen or fitted to suitable data.
Intuition: clustering can leave some regions with fewer defects and others with more. In this model, that variation can increase the fraction of good dies relative to a Poisson model at the same mean defect density; this is a modelling assumption, not a guarantee for every real process.
The Clustering Factor (\(\alpha\)): This parameter controls how “clumped” the defects are. A low \(\alpha\) (e.g., 0.5) means high clustering. A high \(\alpha\) (e.g., 5.0) approaches the Poisson random distribution.
The Equation:
$$Y = \left(1 + \frac{A \cdot D_0}{\alpha}\right)^{-\alpha}$$
The Invisible Cost: Scribe Lines (Saw Streets)
When you look at a silicon wafer, the chips (dies) aren’t touching. They are separated by a grid of empty lanes called Scribe Lines or “Saw Streets.”
What are they? This is the physical space reserved for the diamond saw or laser dicing tool to cut the wafer into individual chips.
What goes in them? Manufacturers often hide test structures (PCM – Process Control Monitors) and alignment marks inside these lanes to monitor the health of the manufacturing process without using up valuable chip area.
Why 0.08mm? The standard scribe width varies by node and dicing technology.
Legacy Nodes: Often used wider lanes (\(100\mu m+\)) for mechanical sawing.
Advanced Nodes: Use narrower lanes (~\(60\mu m – 80\mu m\)) and advanced laser grooving (stealth dicing) to save precious silicon area.
The Economic Impact: wider scribe streets reduce the die footprint density, with the effect depending on chip dimensions, wafer-edge losses and the chosen street width. The financial impact is not a universal dollar amount: calculate it from the actual die count, yield, wafer price and selling-price assumptions for your scenario.
Defect Density (\(D_0\)): The Measure of Maturity
Defect density (\(D_0\)) is commonly expressed as killer defects per square centimetre. It is an important yield input, but not a complete measure of fab health: product design, defect definitions, process layers, systematic errors, edge effects and product-specific screening also matter.
Low (D_0): a lower measured killer-defect density generally improves defect-limited yield for a fixed die area. The value shown here is an input assumption, not a verified current TSMC/Samsung/Intel process metric; actual values vary by product, process, layer and time.
High (D_0): higher defect density reduces modelled yield, especially for large dies. Do not infer an actual node’s ramp stage or product yield from a generic threshold; real process maturity and yields are not universal public constants.
Model notes
Assumptions, units and limits
- Die-area units: the yield equations use die area in cm² and defect density in defects/cm². If die width and height are entered in millimetres, width × height is in mm² and must be divided by 100 to convert to cm² when applying the equation by hand.
- Poisson yield: (Y=e^{-A D_0}), assuming random, independent defects at a uniform mean density.
- Negative Binomial yield: (Y=(1+A D_0/alpha)^{-alpha}), a model that can represent clustering/variation in defect density. The value of (alpha) is an assumption unless fitted to real data.
- Gross dies and scribe streets: any geometric die-per-wafer calculation is an approximation. Actual layouts also depend on edge exclusion, partial dies, reticle fields, test structures, street width and process-specific design rules.
- Cost boundary: because the calculator does not expose separate inputs for package/test, masks and NRE, assembly, logistics or business operating expenses, interpret the result as a wafer-level scenario—not a complete cost-of-goods or corporate gross-margin model.
- Foundry prices: published figures are third-party estimates, not official customer quotes. Prices vary with process flavour, contracts, wafer volume, included services and date. Use a dated supplier quote for procurement or investment decisions.
Methodology note reviewed 29 October 2026. For the assumptions behind the yield models, see the IEEE IC yield overview and this review of yield limits for large chips.
Frequently Asked Questions (FAQ)
How do I find the Die Size?
To get accurate results, you need the physical area of the chip. Here are common estimates for popular hardware:
Nvidia H100: ~814 mm²1
Apple M3 Max: ~480 mm²
AMD MI300X: ~1017 mm² (Chiplet aggregate)
Consumer CPU (Core i9): ~257 mm²
What is a realistic yield rate?
There is no single public yield percentage that applies to every product on a process node. Actual yield depends on die area, circuit complexity, defect definitions, process maturity, design-for-manufacturing and whether the number refers to wafer sort, final test or another stage. Use measured product data when available; otherwise, treat the yield input as a scenario.
In this model, lower yield reduces the number of good dies over which wafer cost is allocated, increasing estimated cost per good die.
Why are wafer costs so high?
Advanced logic wafers can require many complex lithography and process steps, including EUV at leading-edge nodes. Public wafer-price figures are estimates and vary by process flavour, volume, contract and date. Presets in this calculator are not official TSMC, Samsung or Intel quotes; replace them with dated supplier pricing when doing a business case.
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