Check the logic margins
Compare minimum output-high and maximum output-low values against the receiving input thresholds. Supply voltage alone is not enough.
WireUnWired Research Lab · Digital electronics
Logic Level Matcher
Check whether a digital output can reliably drive another device’s input across common 1.8V, 2.5V, 3.3V and 5V logic families. Use the matcher below to shortlist an interface approach, then verify the actual pin thresholds, voltage tolerance, current and timing limits in the manufacturer datasheets.
1.8V logic2.5V logic3.3V logic5V logicPush-pull & open-drain
Before wiring: a nominal voltage match is not proof of compatibility. Check that driver VOH(min) meets receiver VIH(min), driver VOL(max) meets receiver VIL(max), and the receiver’s absolute-maximum input voltage and injection-current limits are respected.
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What this tool helps you assess
From voltage numbers to a safer interface choice.
Match the protocol
Push-pull signals, open-drain buses and bidirectional lines can need different level-shifting methods. Pick based on how the line is driven.
Account for edge speed
Bus capacitance, pull-up resistance, load and propagation delay affect transitions. A solution that works slowly may fail at a higher clock rate.
Review before powering
Use any generated diagram or starter code as a draft. Verify pin direction, supply sequencing, current limits and exact component ratings before connecting hardware.
Engineering guide
Choose a level-shifting method from the datasheet—not just the voltage labels.
Logic families define guaranteed input thresholds and output levels. Compatibility is established from the worst-case values in the relevant device specifications, not from a typical or nominal voltage. Texas Instruments’ voltage-translation application report and translator design guidance explain these margins.
1. Check the guaranteed logic thresholds
Logic HIGH
VOH(min) ≥ VIH(min)The driver’s guaranteed high output must meet or exceed the receiver’s required high-input threshold.
Logic LOW
VOL(max) ≤ VIL(max)The driver’s worst-case low output must stay at or below the receiver’s guaranteed low-input limit.
Also check the input’s absolute-maximum voltage, injection-current limits, power-off behavior and common-ground requirements. Do not assume a 5V-powered device has a 2.4V VIH threshold: some TTL-compatible inputs do, while many CMOS inputs require a higher value. Use the exact part number and operating conditions.
2. Select the approach for the signal type
Resistor divider or buffer
A divider can be appropriate for a single-direction step-down signal when the receiving threshold, input loading, resistor current and RC rise/fall time all check out. It cannot step a signal up and is not a universal translator.
Use a suitable active translator
SPI, UART and other push-pull lines actively drive high and low. Select a translator with the right direction control, data rate, propagation delay, edge performance, voltage range and power-sequencing behavior.
Check pull-ups and bus timing
I²C-style open-drain devices pull low and release the line; pull-ups establish the high level. Check that every device tolerates its bus voltage, and verify pull-up current, capacitance and rise time. A MOSFET shifter can suit some buses, but not every speed or topology.
3. What changes the result for a resistor divider?
For an unloaded divider, the approximate output is Vout = Vin × Rbottom / (Rtop + Rbottom). The real output also depends on receiver input current and other loads. Larger resistor values reduce current but combine with line and input capacitance to slow the edge; smaller values draw more current. Check the worst-case high/low thresholds and the actual waveform.
For open-drain buses, the pull-up resistor and total bus capacitance jointly determine the rise time. Do not apply the divider formula as a substitute for calculating pull-ups and timing.
Safety check: never connect a higher-voltage signal directly to a lower-voltage input unless the exact device documentation explicitly permits that voltage on that pin. “5V tolerant” applies only to pins and conditions specified by the manufacturer. Excess voltage may cause excess input current, latch-up or permanent damage; it is not guaranteed to fail in one specific way.
Sources: Texas Instruments: Basics of Voltage-Level Translation · Texas Instruments: Controlled Voltage Translators/Level-Shifters. Always defer to the datasheets for the selected ICs and boards.
Questions engineers ask
Logic-level matching FAQ
Are all 5V devices compatible with a 3.3V output?
No. Some TTL-compatible 5V inputs have lower high thresholds, while many CMOS inputs require a high level closer to their supply voltage. Compare the driver’s guaranteed VOH(min) with the receiver’s VIH(min) for the exact part and conditions.
Can I connect a 5V signal directly to a 3.3V GPIO?
Only if the exact pin is specified as 5V tolerant under the relevant operating and power-sequencing conditions. Otherwise, the signal can exceed absolute-maximum limits or cause excessive input current, latch-up or damage. Check the datasheet before connecting it.
Is a resistor divider suitable for SPI or UART?
It can work for some one-way, lower-speed signals after checking input thresholds, loading, current and RC edge timing. It is not bidirectional and does not actively restore signal edges. For high-speed or timing-sensitive links, select a translator whose data-rate and direction specifications match the interface.
Is a BSS138 board the right choice for every open-drain or bidirectional signal?
No. MOSFET-based shifters are commonly used for some I²C-style open-drain buses, but suitability depends on pull-ups, bus capacitance, timing, voltage rails and topology. They are not a universal replacement for a directional high-speed translator.
Why should I compare VOH, VIH, VOL and VIL?
They define guaranteed logic-high and logic-low output levels and input thresholds. Check VOH(min) ≥ VIH(min) and VOL(max) ≤ VIL(max), then verify the absolute-maximum input voltage and current limits. See the TI voltage-level translation guide.