Tower Semiconductor Unveils Advanced CPO Foundry Tech for 3D-IC Integration

Tower Semiconductor, a leading Israeli analog semiconductor foundry, has announced a major leap in chip design with the expansion of its 300mm wafer bonding technology. This new advancement enables heterogeneous 3D-IC integration across its industry-leading Silicon Photonics (SiPho) and SiGe BiCMOS platforms, directly targeting the rapidly growing demand for Co-Packaged Optics (CPO) in data centers.

Building on years of expertise in high-volume stacked sensor production, Tower’s enhanced wafer bonding process now allows for the stacking of different wafer technologies—such as photonic and electronic integrated circuits—into a single, ultra-dense 3D-IC. This integration delivers higher performance and richer functionality in a much smaller form factor, making it ideal for next-generation data center and optical networking applications. According to Tower Semiconductor’s official announcement, this is a significant step forward in advancing wafer-scale 3D integration beyond image sensing.

The new technology is fully supported by Cadence design tools, enabling designers to seamlessly co-simulate and co-verify multiple process technologies within a single, unified design environment. This reduces design complexity and increases the likelihood of first-pass success, a crucial advantage for customers developing complex, multi-technology die projects. As Dr. Marco Racanelli, President of Tower Semiconductor, stated:

“With our advanced 300 mm wafer bonding process now supporting multiple wafer technologies on a single 3D-IC, we are enabling customers to achieve new levels of performance, functionality, and integration density needed for CPO.”

The collaboration with Cadence is central, as it extends the Virtuoso Studio Heterogeneous Integration flow to Tower’s platforms, allowing for robust co-design of photonic and electronic subsystems. Ashutosh Mauskar, VP at Cadence, emphasized that this partnership provides a “robust and unified technology flow” for customers, streamlining the path from concept to production.

Why Tower’s 300mm Wafer bond technology for Data Centers and Beyond ?

The demand for compact, high-performance chip solutions is surging as data centers and cloud infrastructure providers seek to handle ever-increasing data loads with greater efficiency and lower power consumption. By enabling the integration of SiPho and SiGe BiCMOS technologies, Tower’s 3D-IC platform allows for the co-packaging of optical and electronic functions, which is critical for reducing latency and power in optical interconnects. This is essential not just for data centers, but also for emerging fields like photonic computing and advanced sensor systems.

Comparing Tower’s New CPO Foundry Technology

What’s Next and Industry Response

The announcement has been met with enthusiasm in the semiconductor sector. Industry leaders from Tower Semiconductor and Cadence have called it a “breakthrough” for multi-technology chip design. While broader market or investor reaction is not yet available—coverage has so far been limited to Israeli and technical outlets—the move is expected to strengthen Tower’s position in the highly competitive analog and photonics foundry market.

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