Silicon Economics Calculator

Silicon economics is a game of high-stakes probability. The difference between a profitable wafer and a massive loss often comes down to three invisible variables: Yield Models, Clustering, and Scribe Lines.

The Battle of Models: Poisson vs. Negative Binomial

In our simulator, you will notice a toggle between two yield models. This isn’t just a math trick; it represents the difference between theoretical stats and factory reality.

The Poisson Model (The “Rain” Theory)

The Poisson distribution assumes that defects are distributed completely randomly across the wafer, like raindrops falling on a sidewalk.

• The Logic: If you have 100 defects and 100 chips, the Poisson model assumes those defects will spread out and kill a large number of chips.

• When to use it: This model is often too pessimistic for large dies. It is best used for calculating yield on mature, stable processes where defects truly are random and rare.

• The Equation:

  $$Y = e^{-A \cdot D_0}$$

The Negative Binomial Model (The “Cluster” Theory)

This is the industry standard (often called the Stapper model). In the real world, defects tend to “cluster.” A spec of dust might cause 5 defects in one tiny corner, or a chemical splash might ruin a specific zone.

• The Logic: If those same 100 defects are clustered together in one spot, they might destroy that one area completely, but leave the rest of the wafer pristine. Paradoxically, clustering increases yield because the defects “overlap” on chips that are already dead.

• The Clustering Factor ($\alpha$): This parameter controls how “clumped” the defects are. A low $\alpha$ (e.g., 0.5) means high clustering. A high $\alpha$ (e.g., 5.0) approaches the Poisson random distribution.

• The Equation:

  $$Y = \left(1 + \frac{A \cdot D_0}{\alpha}\right)^{-\alpha}$$
   

The Invisible Cost: Scribe Lines (Saw Streets)

When you look at a silicon wafer, the chips (dies) aren’t touching. They are separated by a grid of empty lanes called Scribe Lines or “Saw Streets.”

• What are they? This is the physical space reserved for the diamond saw or laser dicing tool to cut the wafer into individual chips.

• What goes in them? Manufacturers often hide test structures (PCM – Process Control Monitors) and alignment marks inside these lanes to monitor the health of the manufacturing process without using up valuable chip area.

• Why 0.08mm? The standard scribe width varies by node and dicing technology.

  • Legacy Nodes: Often used wider lanes ($100\mu m+$) for mechanical sawing.

  • Advanced Nodes: Use narrower lanes (~$60\mu m – 80\mu m$) and advanced laser grooving (stealth dicing) to save precious silicon area.

• The Economic Impact: On a 300mm wafer, a wider scribe line can reduce the total gross die count by 1-3%. That might sound small, but on a $30,000 wafer, that is nearly $1,000 of lost revenue just from the gap between chips.

Defect Density ($D_0$): The Measure of Maturity

The Defect Density ($D_0$) is the number of “killer defects” per square centimeter. It is the single most important metric for a fab’s health.

• $D_0 < 0.1$ (Mature): This is the gold standard. TSMC’s 5nm and 7nm nodes are likely operating in this range. At this level, you can profitably manufacture massive chips (like NVIDIA GPUs or Apple M-series processors).

• $D_0 > 0.5$ (Risk Production): When a new node (like 2nm) first comes online, the defect density is high. Yields plummet. This is why the first chips on a new node are always small (like smartphone SoCs)—because a small chip has a statistical chance of “dodging” the defects, whereas a large chip will almost certainly get hit.